The present invention relates to direct memory access in a data processing system, and specifically to controlling direct memory access using a user-programmable algorithm.
Direct Memory Access (DMA) controllers are used in computer systems to offload repetitive data movement tasks from a processor in a data processing system. As the demand for increased performance of the processor, or central processing unit (CPU), increases so does the need for high-throughput, flexible DMAs that work well with these processors. Original DMA controllers (DMACs) used only registers or memory storage devices to specify source, destination, and length of data to be transferred. The DMAC was coupled to only one source device. Soon the need to carry out simultaneous block transfers led to the development of multi-channel DMACs that achieved the effect of performing several data movements simultaneously. As data transfer rates continued to increase, set up, service and interrupt overhead for the DMACs became too high, especially when the DMAC was programmed for a single contiguous block of memory per interrupt.
To overcome these overhead issues, descriptor-based DMACs were introduced. As the computer system complexity increased, so the DMACs increased in complexity. Today, some DMACs use a dedicated processor to perform such complex functions. The dedicated processor, or coprocessor, is often based on a reduced instruction set computer (RISC) methodology. Such coprocessors operate on increasingly complex protocols, and often provide algorithmic support, such as digital filtering operations. The algorithmic support is critical to many applications where data movement and calculation rates are high. This is particularly true of entertainment applications, such as video, graphic and audio applications, and is also important in areas such as audio and visual decompression calculations. While the need for flexible algorithmic manipulation of data by the DMAC increases, the coprocessor becomes less attractive as it operates on a data-structure descriptor architecture which has limited flexibility and it can not achieve the high performance of the dedicated state machine of a traditional DMAC.
When a process in a DMA controller (DMAC) is interrupted, it is expedient and often necessary to save information relating to the current process to allow the process to continue after the interruption is resolved. This information is referred to as the xe2x80x9ccontext.xe2x80x9d Registers, stacks, and arrays are allocated for context storing. The information stored may be rather large, including address, control and status information. This introduces delays to the operation of the DMA for storing the information and later retrieving the information. Additionally, storage space requirements may become quite large impacting the size of the DMAC.
Therefore, there is a need for a method to control a DMAC that allows algorithmic support using descriptors that define DMA algorithms instead of data structures, which provides an efficient context storing mechanism. There is further a need for a DMAC that has a variety of functions and thereby increase the efficiency and performance of a DMA.